News

The workshop proceedings have been published by VDE-Verlag (available here).
They will be indexed by IEEE Xplore.

Detailed program available.
Accepted papers and invited speakers announced.

go to the FSP 2016 EasyChair page to submit
https://www.easychair.org/conferences/?conf=fsp2016

Proceedings will be published by VDE-Verlag and indexed by IEEE Xplore.

Overview and Scope

The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers. Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists. With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken.

The FSP Workshop aims at bringing researchers and experts from both academia and industry together to discuss and exchange the latest research advances and future trends. This includes high-level compilation and languages, design automation tools that raise the abstraction level when designing for (heterogeneous) FPGAs and reconfigurable systems and standardized target platforms. This will in particular put focus on the requirements of software developers and application engineers. In addition, a distinctive feature of the workshop will be its cross section through all design levels, ranging from programming down to custom hardware. Thus, the workshop is targeting all those who are interested in understanding the big picture and the potential of domain-specific computing and software-driven FPGA development. In addition, the FSP Workshop shall facilitate collaboration of the different domains.

Topics of the FSP Workshop include, but are not limited to:

• High-level synthesis (HLS) and domain-specific languages (DSLs) for FPGAs and heterogeneous systems
• Mapping approaches and tools for heterogeneous FPGAs
• Support of hard IP blocks such as embedded processors and memory interfaces
• Development environments for software engineers (automated tool flows, design frameworks and
     tools, tool interaction)
• FPGA virtualization (design for portability, resource sharing, hardware abstraction)
• Design automation technologies for multi-FPGA and heterogeneous systems
• Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility,
     reliability, or programmability
• Operating system services for FPGA resource management, reliability, security
• Target hardware design platforms (infrastructure, drivers, portable systems)
• Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics)
• Applications (e.g., embedded computing, signal processing, bio informatics, big data,
     database acceleration) using C/C++/SystemC-based HLS, OpenCL, OpenSPL, etc.
• Directions for collaborations (research proposals, networking, Horizon 2020)

Previous Editions

• FSP Workshop 2014
• FSP Workshop 2015

Call for Papers

Download as PDF document.

Paper submission

Perspective authors are invited to submit original contributions (up to eight pages) or extended abstracts describing work-in-progress or position papers (not exceeding two pages). All papers should be formatted as follows: A4 or US Letter size, PDF file format (must not have Adobe Document Protection or Document Security enabled and must have all fonts embedded), double column, single spaced, Times or equivalent font of minimum 10pt. We recommend that you use the proceedings templates for LaTeX and Word formats provided by VDE-Verlag (https://www.vde-verlag.de/proceedings-en/type-instructions.html).
All submissions have to be sent via the conference management system EasyChair. Please set up your own personal account if you do not already own an EasyChair account.

Publications

The proceedings of this workshop containing all accepted full papers will be published by VDE-Verlag (Germany) and will be indexed by IEEE Xplore. Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is due.

Important dates

Submission deadline:June 30, 2016 extended to July 7, 2016
Notification of acceptance:July 21, 2016
Camera-ready final version:July 28, 2016

Registration Information

Please visit the FPL 2016 homepage (http://fpl2016.org/#registration) for registration.

Program

Download program as PDF document.

Invited Speakers

Abstract:
Recent methodologies for FPGA design are centered on high-level synthesis (HLS) tools and leverage software programming languages such as OpenCL, C and C++. Yet, these methodologies often fall short of addressing many of system-level design challenges. To truly enable software programmers, a comprehensive approach is required, covering programming models, hardware infrastructure, 3rd party IP integration, hardware-software communication stack, and last, but not least, the critical debug challenge. This talk will present a novel and comprehensive approach to software-defined FPGA computing system design.

Speaker's bio:
Gael Paul has over 20 years of experience in the Electronic Design Automation (EDA) and semiconductor fields. Gael is a recognized technologist that uniquely combines product architecture & development, chip design and field experience.
Gael is CTO and Chief Architect of the QuickPlay platform at PLDA. He has spent the last five years leading a multi-national and multi-talented team developing QuickPlay, a disruptive innovation that enables software programmers to develop FPGA-based systems in days.
Prior to joining PLDA, Gael was Vice President Software Engineering & Product Development at Achronix, a US fabless semiconductor company that developed a disruptive asynchronous FPGA solution. He architected and built the entire software flow from the ground-up, hired a world-class development team, and established OEM partnerships with key suppliers. Gael was also instrumental in defining the methodology to map synchronous designs to asynchronous hardware.
Before joining Achronix, Gael was Director of FPGA Synthesis Products at Synplicity, a US EDA company that was the world leader in FPGA synthesis before being acquired by Synopsys. He was responsible for defining product direction, product architecture and for managing the development process of the FPGA product line. Prior to joining the engineering organization, Gael spent several years as European Technical Specialist in the European Sales Organization.
Prior to joining Synplicity, Gael was a Senior Design Consultant at Cadence Design Services, where he designed several ASICs and FPGAs for large telecommunication companies throughout Europe.
Gael authored or co-authored several patents in the field of high-level synthesis, logic synthesis, optimizations and asynchronous circuits. Gael is also the inventor of the IP Encryption scheme that became the IEEE 1735 standard. Gael received an M.S.E.E., Summa Cum Laude, from ESIEE in Paris, France, in collaboration with the University of Texas at Austin.

Abstract:
The reconfigurable computing community has long had the dream that software programmers will be able to use Field-Programmable Gate Arrays (FPGAs) as computing devices. With high-level synthesis (HLS) now reaching a level of quality that reasonable hardware can be generated from languages such as C, C++ and OpenCL, it would seem that having software programmers use FPGAs for computing is much closer to reality. HLS certainly overcomes a significant and important hurdle, but there are other large barriers that get very little attention for computing with FPGAs. Software programmers generally work with many abstractions, as for example with I/O to the network, and these abstractions provide important properties, such as portability and scalability. Below these abstractions, there is a significant amount of middleware infrastructure to enable and support the abstractions. Some standardization is required in the underlying platforms, particularly amongst hardware vendors, to make it easier to build, maintain and enable the infrastructure. This paper examines many issues that are often not considered when thinking about computing using FPGAs: the kinds of abstractions required, how they can be supported, what standards are needed, and the need for open standards to support an ecosystem that supports FPGAs for computing and, ultimately, an environment where software programmers can easily use FPGAs.

Speaker's bio:
Paul Chow is a Professor in the Department of Electrical and Computer Engineering at the University of Toronto where he holds the Dusan and Anne Miklas Chair in Engineering Design. Prior to joining UofT in 1988 he was at the Computer Systems Laboratory at Stanford University, Stanford, CA, as a Research Associate, where he was a major contributor to an early RISC microprocessor design called MIPS-X, one of the first microprocessors with an on-chip instruction cache and the root of many concepts used in processors today. His research interests include high performance computer architectures, reconfigurable computing, embedded and application-specific processors, and field-programmable gate array architectures and applications.

Abstract:
This talk describes a new, open-source framework for designing with Xilinx Zynq devices, a class of All Programmable Systems on Chip (APSoCs) which integrates multiple processors and Field Programmable Gate Arrays (FPGAs) into single integrated circuits.
The main goal of framework is to make it easier for designers of embedded systems to exploit the unique benefits of APSoCs in their applications. Specifically, it enables the architects, engineers and programmers who design embedded systems to exploit the capabilities of Zynq APSoCs without having to use ASIC-style, CAD tools to design programmable logic circuits. Instead the APSoC is programmed in Python and the code is developed and tested directly on the embedded system. The programmable logic circuits are imported as hardware libraries and programmed through their APIs, in essentially the same way that software libraries are imported and programmed.
The framework combines four main elements:
- the use of a high-level productivity language, Python in this case
- Python-callable hardware libraries based on FPGA overlays
- a web-based architecture incorporating the open-source Jupyter Notebook infrastructure served from Zynq's embedded processors
- Jupyter Notebook's client-side, web apps
The result is a programming environment that is web-centric so it can be accessed from any browser on any computing platform or operating system. It enables software programmers to work at higher levels of design abstraction and to re-use both software and hardware libraries. The framework is inherently extensible and integrates coherently with hardware–dependent code written in C and C++.
The talk concludes with a live demonstration, an outline of areas for continued development, and a call for community participation.

Speaker's bio:
Patrick Lysaght is a Senior Director in Xilinx Research Labs, San Jose, California. He leads a group whose research interests include system-level performance analysis, modelling, and design for heterogeneous, reconfigurable architectures. He is especially interested in emerging design methodologies based on open source technologies. Patrick also directs the worldwide operation of the Xilinx University Program (XUP). Before joining Xilinx, he held positions as a senior lecturer at the University of Strathclyde (Glasgow) and at the Institute for System Level Integration (Livingston, Scotland). He started his career in research and development with Hewlett Packard (Edinburgh) before going on to hold a number of technical and marketing positions. Patrick has co-authored more than fifty technical papers, co-edited two books on programmable logic and holds ten US patents. He has served on the technical committees of numerous international conferences and is chairman of the steering committee for FPL, the world’s largest conference dedicated to field programmable logic. Two of his papers on dynamically reconfigurable logic feature among the most significant research papers of the first 25 years of FPL. Patrick holds a BSc (Electronic Systems) from the University of Limerick, Ireland and an MSc degree (Digital Techniques) from Heriot-Watt University in Edinburgh, Scotland.

Organization

Andreas Koch, Technische Universität Darmstadt, Germany
Markus Weinhardt, Osnabrück University of Applied Sciences, Germany

Christian Hochberger, Technische Universität Darmstadt, Germany

Hideharu Amano, Keio University, Japan
Jason H. Anderson, University of Toronto, Canada
Tobias Becker, Maxeler Technologies, UK
João M. P. Cardoso, University of Porto, Portugal
Sunita Chandrasekaran, University of Delaware, USA
Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Dirk Koch, The University of Manchester, UK
Miriam Leeser, Northeastern University, USA
Walid Najjar, University of California Riverside, USA
Marco Platzner, University of Paderborn, Germany
Christian Plessl, University of Paderborn, Germany
Dan Poznanovic, Cray Inc., USA
Olivier Sentieys, University of Rennes, France
Dirk Stroobandt, Ghent University, Belgium
Gustavo Sutter, Autonomous University of Madrid, Spain
Peter Yiannacouras, Altera Corp., Canada
Daniel Ziener, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany

fsp2016@easychair.org