Overview and Scope
The aim of this workshop is to make FPGA and reconfigurable
technology accessible to software programmers.
Despite their frequently proven power and performance benefits,
designing for FPGAs is mostly an engineering discipline carried out by
highly trained specialists.
With recent progress in high-level synthesis, a first important
step towards bringing FPGA technology to potentially millions of
software developers was taken.
In the second edition of the FSP workshop, we will in particular
focus on success stories where FPGAs had been exploited by software
engineers.
The FSP Workshop aims at bringing researchers and experts from
both academia and industry together to discuss and exchange the latest
research advances and future trends.
This includes high-level compilation and languages, design
automation tools that raise the abstraction level when designing for
(heterogeneous) FPGAs and reconfigurable systems and standardized target
platforms.
This will in particular put focus on the requirements of software
developers and application engineers.
In addition, a distinctive feature of the workshop will be its
cross section through all design levels, ranging from programming down
to custom hardware.
Thus, the workshop is targeting all those who are interested in
understanding the big picture and the potential of domain-specific
computing and software-driven FPGA development.
In addition, the FSP Workshop shall facilitate collaboration of
the different domains.
Topics of the FSP Workshop include, but are not limited to:
- High-level synthesis (HLS) and domain-specific languages (DSLs) for FPGAs and heterogeneous systems
- Mapping approaches and tools for heterogeneous FPGAs
- Support of hard IP blocks such as embedded processors and memory interfaces
- Development environments for software engineers (automated tool flows, design frameworks and
tools, tool interaction)
- FPGA virtualization (design for portability, resource sharing, hardware abstraction)
- Design automation technologies for multi-FPGA and heterogeneous systems
- Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility,
reliability, or programmability
- Operating system services for FPGA resource management, reliability, security
- Target hardware design platforms (infrastructure, drivers, portable systems)
- Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics)
- Applications (e.g., embedded computing, signal processing, bio informatics, big data,
database acceleration) using C/C++/SystemC-based HLS, OpenCL, OpenSPL, etc.
- Directions for collaborations (research proposals, networking, Horizon 2020)
Proceedings
Access ePrint Proceedings here: http://arxiv.org/html/1508.06320
Previous Editions
FSP Workshop 2014
Call for Papers
Download as PDF document.
Paper submission
Perspective authors are invited to submit original contributions
(up to six pages) or extended abstracts describing work-in-progress or
position papers (extended abstracts should not exceed two pages).
All papers should be submitted in PDF file format following
the standard IEEE conference template (http://www.ieee.org/conferences_events/conferences/publishing/templates.html).
Papers may or may not hide author names and affiliation for optional blind reviewing.
All submissions have to be sent via the conference management system EasyChair.
Please set up your own personal account if you do not already own an EasyChair account.
Publications
Accepted papers will be included in an ePrint proceedings volume with Open Access.
Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is due.
Presentation formats
We are seeking contributions for presentation as oral papers (talk) and posters.
Note that the presentation format is independent of the paper
length (i.e., regular or short paper).
While you will be asked to indicate your preferred presentation
format when submitting a paper, the program committee may request an
alternative format be considered.
The program committee will allocate the format of presentations,
taking into account the preference of authors and the balance of the
program.
Important dates
Submission deadline:June 30, 2015 extended to July 10, 2015 (strict)
Notification of acceptance:July 31, 2015
Camera-ready final version:August 14, 2015
Registration Information
Please visit the FPL 2015 homepage (http://www.fpl2015.org/?page=registration) for registration.
Program and Proceedings
Tuesday September 1, 2015
9:00 – 9:10
Welcome and Introduction
Dirk Koch, Tobias Becker, Frank Hannig, and Daniel Ziener
9:10 – 10:10
Keynote Speech 1
10:10 – 10:30
Fast-Forward Presentation of Posters
10:30 – 11:00
Coffee Break and Posters
11:00 – 12:30
Session 1: HLS Tooling
Chair: Frank Hannig
13:30 – 14:30
Keynote Speech 2
14:30 – 15:00
Session 2: Mapping for Stream Processing Applications
Chair: Tobias Becker
15:00 – 15:30
Coffee Break
15:30 – 17:00
Session 3: Heterogeneous Computing – From Embedded to Cloud
Chair: George Constantinides
Keynote speakers:
Guy Lemieux, Founder, CEO, and CTO of VectorBlox Computing Inc., Vancouver, Canada
"Application Acceleration with the VectorBlox MXP"
Abstract:
Many FPGA applications have internal data parallelism that
can be sped up by a variety of techniques. In this talk, we will explore
how we can speed them up with vector processing. In particular, using a
counter vision application, we will demonstrate several features in the
VectorBlox MXP processor that we have added to get massive speedup
versus onboard ARM processors. This is done through a combination of
algorithm adaptations, data size reductions, clever use of conditional
execution, and the addition of custom instructions. We will demonstrate
how a software compilation approach using soft processors in an FPGA
can outperform hard processors.
Iakovos Panourgias, EPCC, University of Edinburgh, UK
"Porting of a Particle Transport Code to an FPGA"
Abstract:
In this talk, we will discuss how software programmers can
use recent advances for porting applications to FPGAs. We will discuss
how writing code for FPGAs is hard. Using a particle transport code, we
will show how a software programmer can create an FPGA port without
writing a single line of VHDL and how to use performance models to
estimate the runtime of the port. We will also show how minor algorithm
modifications and data re-ordering and sizes affect performance of FPGA
ports.
Organization
General Co-Chairs
Tobias Becker, Maxeler Technologies, UK
Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Dirk Koch, The University of Manchester, UK
Daniel Ziener, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Program Committee
Hideharu Amano, Keio University, Japan
Jason H. Anderson, University of Toronto, Canada
Gordon Brebner, Xilinx Inc., USA
João M. P. Cardoso, University of Porto, Portugal
Sunita Chandrasekaran, University of Houston, USA
Andreas Koch, Technical University of Darmstadt, Germany
Miriam Leeser, Northeastern University, USA
Walid Najjar, University of California Riverside, USA
Gael Paul, PLDA, France
Marco Platzner, University of Paderborn, Germany
Dan Poznanovic, Cray Inc., USA
Rodric Rabbah, IBM Research, USA
Olivier Sentieys, University of Rennes, France
Dirk Stroobandt, Ghent University, Belgium
Gustavo Sutter, Autonomous University of Madrid, Spain
David Thomas, Imperial College London, UK
Kazutoshi Wakabayashi, NEC Corp., Japan
Markus Weinhardt, Osnabrück University of Applied Sciences, Germany
Peter Yiannacouras, Altera Corp., Canada
Contact
fsp2015@easychair.org