News

The workshop proceedings have been published by VDE-Verlag (available here).
They are also available in IEEE Xplore.

The program has been updated.

The detailed program is available.

https://www.fpl2018.org/registration/

Go to the FSP 2018 EasyChair page to submit.
https://www.easychair.org/conferences/?conf=fsp2018

Overview and Scope

The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers. Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists. With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken.

The FSP Workshop aims at bringing researchers and experts from both academia and industry together to discuss and exchange the latest research advances and future trends. This includes high-level compilation and languages, design automation tools that raise the abstraction level when designing for (heterogeneous) FPGAs and reconfigurable systems and standardized target platforms. This will in particular put focus on the requirements of software developers and application engineers. In addition, a distinctive feature of the workshop will be its cross section through all design levels, ranging from programming down to custom hardware. Thus, the workshop is targeting all those who are interested in understanding the big picture and the potential of domain-specific computing and software-driven FPGA development. In addition, the FSP Workshop shall facilitate collaboration of the different domains.

Topics of the FSP Workshop include, but are not limited to:

• High-level synthesis (HLS) and domain-specific languages (DSLs) for FPGAs and heterogeneous systems
• Mapping approaches and tools for heterogeneous FPGAs
• Support of hard IP blocks such as embedded processors and memory interfaces
• Development environments for software engineers (automated tool flows, design frameworks and
     tools, tool interaction)
• FPGA virtualization (design for portability, resource sharing, hardware abstraction)
• Design automation technologies for multi-FPGA and heterogeneous systems
• Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility,
     reliability, or programmability
• Operating system services for FPGA resource management, reliability, security
• Target hardware design platforms (infrastructure, drivers, portable systems)
• Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics)
• Applications (e.g., embedded computing, signal processing, bio informatics, big data,
     database acceleration) using C/C++/SystemC-based HLS, OpenCL, OpenSPL, etc.
• Directions for collaborations (research proposals, networking, Horizon 2020)

Previous Editions

• FSP Workshop 2014
• FSP Workshop 2015
• FSP Workshop 2016
• FSP Workshop 2017

Call for Papers

Download as PDF document.

Paper submission

Perspective authors are invited to submit original contributions (up to eight pages) or extended abstracts describing work-in-progress or position papers (not exceeding two pages). All papers should be formatted as follows: A4 or US Letter size, PDF file format (must not have Adobe Document Protection or Document Security enabled and must have all fonts embedded), double column, single spaced, Times or equivalent font of minimum 10pt. We recommend that you use the proceedings templates for LaTeX and Word formats provided by VDE-Verlag (https://www.vde-verlag.de/proceedings-en/type-instructions.html).
All submissions have to be sent via the conference management system EasyChair. Please set up your own personal account if you do not already own an EasyChair account.

Publications

The proceedings of this workshop containing all accepted papers are planned to be published by VDE-Verlag (Germany) and are planned to be indexed by IEEE Xplore. Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is due.

Important dates

Submission deadline:May 27, 2018 extended to June 17, 2018
Notification of acceptance:July 1, 2018 extended to July 9, 2018
Camera-ready final version:July 15, 2018 extended to July 25, 2018

Registration Information

Please visit the FPL 2018 homepage (https://fpl2018.org/registration/) for registration.

Program

Download program as PDF document.

Invited Speakers

Abstract:
It is widely recognized that traditional hardware description languages (VHDL, Verilog) have poor abstraction mechanisms, turning FPGA design into a cumbersome activity. To tackle this problem, High Level Synthesis (HLS) systems are developed which generate VHDL or Verilog from a more mainstream programming language such as C++, Java, etcetera. However, the imperative basis of mainstream programming languages does not fit hardware design well, mainly because of the problem to parallelize sequential code. As a consequence, an FPGA often is not used optimally and the details of a design are not under the control of the designer.
Alternatively, CλaSH offers an FPGA design environment based on the functional programming language Haskell. Because of its mathematical nature, a functional specification is fundamentally parallel and thus closer to hardware. CλaSH gives full control over the details of an FPGA design, and offers cycle accurate simulation and test possibilities at the top level of a design.
During this talk we will introduce CλaSH by example and discuss some powerful abstraction mechanisms such as type derivation, higher order functions, and the definability of domain specific embedded languages. We will also show the possibility of formally transforming a design for better performance.

Speaker's bio:
Jan Kuper studied logic and mathematics at the University of Twente, where he got his Master degree (with honours) in 1985. In 1994 he received his PhD degree on the foundations of mathematics and computer science. He developed a theory of partial functions and generalized it to a theory of binary relations, which both are strong enough to be a foundation of mathematics.
He worked as a lecturer at the University of Leiden, as a researcher at the University of Nijmegen, and as an assistant professor at the university of Twente. His main fields of interest developed from philosophical and mathematical logic, to functional programming and and to exploiting functional languages for hardware specification. Based on the functional programming language Haskell he initiated the development of CλaSH. In 2016 he co-founded (together with Dr. Christiaan Baaij) the company QBayLogic for hardware design, in particular FPGAs, with CλaSH.
He published on the foundations of mathematics, lambda calculus, logic for artificial intelligence, specification languages for FPGA design, and on energy reduction for computer architectures.

Abstract:
Since FPGAs made their way into major public clouds and off-the-shelf server products by data center suppliers, FPGA hardware is now available to a significantly increased number of new use cases. While the abundance of FPGA hardware is the first step, there still exists a gap between applications and the chip technology. In this talk, we look at this gap from two angles: Firstly, FPGA development in the presence of a plethora of new, very diverse use cases requires higher levels of abstractions of the design entry (compared to RTL) more than ever. We will share our experience with several state-of-the-art high-level synthesis tool flows. Secondly, the level of abstraction from the hardware platform must be raised also from the viewpoint of operating an FPGA-based solution in a commercial software application. We will present our learnings from pitching FPGA technology to customers who have no knowledge about hardware accelerator technology, but who are in need of application acceleration.

Speaker's bio:
Felix Winterstein is the CEO of Xelera Technologies GmbH. Xelera’s software provides acceleration to applications in the data center and in the cloud, predominantly leveraging FPGA technology. Prior to joining Xelera, Felix worked as a research associate in the Circuits and Systems Group at Imperial College London, and as an electronic engineer at the European Space Agency. He received his PhD degree from Imperial College in 2016 and his Master’s degree (Dipl.-Ing.) from RWTH Aachen University in 2009.

Organization

Andreas Koch, Technische Universität Darmstadt, Germany
Markus Weinhardt, Osnabrück University of Applied Sciences, Germany

Christian Hochberger, Technische Universität Darmstadt, Germany

Hideharu Amano, Keio University, Japan
Jason H. Anderson, University of Toronto, Canada
João M. P. Cardoso, University of Porto, Portugal
Sunita Chandrasekaran, University of Delaware, USA
Paul Chow, University of Toronto, Canada
Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg, Germany
Tobias Kenter, University of Paderborn, Germany
Dirk Koch, University of Manchester, UK
Miriam Leeser, Northeastern University, USA
Janarbek Matai, COGNEX, USA
Gael Paul, PLDA, France
Marco Platzner, University of Paderborn, Germany
Dan Poznanovic, Cray Inc., USA
Gustavo Sutter, Autonomous University of Madrid, Spain
Zain Ul-Abdin, Halmstad University, Sweden
Rüdiger Willenberg, Mannheim University of Applied Sciences, Germany
Daniel Ziener, University of Twente, Netherlands

fsp2018@easychair.org