News

The workshop proceedings have been published by VDE-Verlag (available here).
They are also available in IEEE Xplore.

Presentation slides are available for download without password.

The detailed program is available.

https://www.fpl2017.org/registration/

Due to authors' requests, the submission deadline has been finally extended to June 25, 2017.

Go to the FSP 2017 EasyChair page to submit.
https://www.easychair.org/conferences/?conf=fsp2017

Overview and Scope

The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers. Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists. With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken.

The FSP Workshop aims at bringing researchers and experts from both academia and industry together to discuss and exchange the latest research advances and future trends. This includes high-level compilation and languages, design automation tools that raise the abstraction level when designing for (heterogeneous) FPGAs and reconfigurable systems and standardized target platforms. This will in particular put focus on the requirements of software developers and application engineers. In addition, a distinctive feature of the workshop will be its cross section through all design levels, ranging from programming down to custom hardware. Thus, the workshop is targeting all those who are interested in understanding the big picture and the potential of domain-specific computing and software-driven FPGA development. In addition, the FSP Workshop shall facilitate collaboration of the different domains.

Topics of the FSP Workshop include, but are not limited to:

• High-level synthesis (HLS) and domain-specific languages (DSLs) for FPGAs and heterogeneous systems
• Mapping approaches and tools for heterogeneous FPGAs
• Support of hard IP blocks such as embedded processors and memory interfaces
• Development environments for software engineers (automated tool flows, design frameworks and
     tools, tool interaction)
• FPGA virtualization (design for portability, resource sharing, hardware abstraction)
• Design automation technologies for multi-FPGA and heterogeneous systems
• Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility,
     reliability, or programmability
• Operating system services for FPGA resource management, reliability, security
• Target hardware design platforms (infrastructure, drivers, portable systems)
• Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics)
• Applications (e.g., embedded computing, signal processing, bio informatics, big data,
     database acceleration) using C/C++/SystemC-based HLS, OpenCL, OpenSPL, etc.
• Directions for collaborations (research proposals, networking, Horizon 2020)

Previous Editions

• FSP Workshop 2014
• FSP Workshop 2015
• FSP Workshop 2016

Call for Papers

Download as PDF document.

Paper submission

Perspective authors are invited to submit original contributions (up to eight pages) or extended abstracts describing work-in-progress or position papers (not exceeding two pages). All papers should be formatted as follows: A4 or US Letter size, PDF file format (must not have Adobe Document Protection or Document Security enabled and must have all fonts embedded), double column, single spaced, Times or equivalent font of minimum 10pt. We recommend that you use the proceedings templates for LaTeX and Word formats provided by VDE-Verlag (https://www.vde-verlag.de/proceedings-en/type-instructions.html).
All submissions have to be sent via the conference management system EasyChair. Please set up your own personal account if you do not already own an EasyChair account.

Publications

The proceedings of this workshop containing all accepted papers will be published by VDE-Verlag (Germany) and will be indexed by IEEE Xplore. Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is due.

Important dates

Submission deadline:May 28, 2017 extended to June 25, 2017 (final extension)
Notification of acceptance:June 20, 2017 extended to July 30, 2017
Camera-ready final version:July 10, 2017 extended to August 8, 2017

Registration Information

Please visit the FPL 2017 homepage (https://www.fpl2017.org/registration/) for registration.

Program

Download program as PDF document.

Invited Speakers

Abstract:
The ever increasing density of logic and decreasing cost of silicon leads to situations where embedded software enables all kind of smart solutions in conservative or non-trivial application domains. But it also leads to non-trivial design implementations. Especially in the specific domains as fault-tolerant computing, real-time high speed control, bio-metric data processing, etc. The use of FPGA devices in a heterogeneous context with processors is becoming widely accepted in these applications as it is a more power-efficient and more flexible solution compared to GPU based acceleration. However, the programmability as well as the programming model can form an issue here. During this talk the capabilities of, experiences with and faced challenges of hybrid FPGA/CPU systems are discussed in a domain specific context addressing the specific programming and verification needs from a systems and software perspective.

Abstract:
Reconfigurable fabrics, especially FPGAs, have become very sophisticated and complex computing platforms. Their customization features, large scale computing power, heterogeneity, and reconfigurability, make them computing platforms of choice in many application domains, from high-performance to embedded computing. FPGAs are able to provide hardware acceleration to algorithms and complete system solutions with low cost and efficient performance/energy tradeoffs.
Although the significant improvements seen in high-level synthesis (HLS), typically applications source code needs substantial code restructuring/refactoring in order that HLS tools are able to achieve efficient FPGA implementations. This is neither a simple task for software developers nor for compilers and has become an important line of research.
This presentation will start by motivating the investment on source to source compilers and then by identifying some of the problems regarding code restructuring. We will focus on the code restructuring improvements over the last years, the trends, the challenges, and on the aspects that make code restructuring an exciting research subject. Finally, we will highlight recent achievements and our approaches aimed at providing automatic code restructuring.

Speaker's bio:
João M. P. Cardoso received an Electronics Eng. degree from the Univ. of Aveiro in 1993, and an MSc and a PhD degree in Electrical and Computer Eng. from the Technical Univ. of Lisbon (IST/UTL), Lisbon, Portugal, in 1997 and 2001, respectively. He is currently Full Professor at the Dep. of Informatics Eng., Faculty of Eng. of the Univ. of Porto, Porto, Portugal and a research member of INESC-TEC. Before, he was with the IST/UTL (2006-2008), a senior researcher at INESC-ID (2001-2009), and with the Univ. of Algarve (1993-2006). In 2001/2002, he worked for PACT XPP Tech., Inc., Munich, Germany. He has participated in the organization and he served as a Program Committee member for many Int’l Conferences. He has (co-)authored over 200 scientific publications (including books, journal/conference papers and patents) on subjects related to compilers, embedded systems, and reconfigurable computing. He was co-scientific coordinator of the FP7 project REFLECT (2010-2012) and coordinator of various national projects. He is a senior member of IEEE, IEEE Computer Society and a senior member of ACM. His research interests include compilation techniques, domain-specific languages, reconfigurable computing, application-specific architectures, and high-performance embedded computing.

Webpage: http://www.fe.up.pt/~jmpc
DBLP: http://dblp.uni-trier.de/pers/hd/c/Cardoso:Jo=atilde=o_M=_P=
ORCID: http://orcid.org/0000-0002-7353-1799
Email: jmpc@acm.org

Organization

Andreas Koch, Technische Universität Darmstadt, Germany
Markus Weinhardt, Osnabrück University of Applied Sciences, Germany

Christian Hochberger, Technische Universität Darmstadt, Germany

Hideharu Amano, Keio University, Japan
Jason H. Anderson, University of Toronto, Canada
Tobias Becker, Imperial College, London, UK
João M. P. Cardoso, University of Porto, Portugal
Sunita Chandrasekaran, University of Delaware, USA
Paul Chow, University of Toronto, Canada
Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg, Germany
Tobias Kenter, University of Paderborn, Germany
Dirk Koch, The University of Manchester, UK
Miriam Leeser, Northeastern University, USA
Janarbek Matai, University of California, USA
Walid Najjar, University of California Riverside, USA
Gael Paul, PLDA, France
Marco Platzner, University of Paderborn, Germany
Dan Poznanovic, Cray Inc., USA
Gustavo Sutter, Autonomous University of Madrid, Spain
Zain Ul-Abdin, Halmstad University, Sweden
Rüdiger Willenberg, Mannheim University of Applied Sciences, Germany
Peter Yiannacouras, Altera Corp., Canada
Daniel Ziener, Friedrich-Alexander University Erlangen-Nürnberg, Germany

fsp2017@easychair.org